Circuits fabricated with silicon-on-insulator (SOI) substrates show reduced parasitic capacitance compared to bulk or epitaxial substrates. Less capacitance results in lower power consumption and higher speed. SOI devices are also useful for memory applications because of their high-radiation single-event-upset (SEU) immunity. Wafer bonding is one method for manufacturing SOI substrates, which involves two silicon wafers bonded and most of the silicon from one wafer is removed and the device is built into the remaining silicon over the now-buried oxide. FIG. 1A is a simplified illustration of a typical wafer bonding method, which begins with a first Wafer A (also known as the donor wafer) and a second Wafer B (as known as the handle wafer). Wafer A is oxidized to form what will become the buried oxide. In a thermal oxidizing environment, both the topside and backside of Wafer A can form oxidized layers, although only the topside is used for wafer bonding. Wafer A is then implanted with an ion, such as H+ below the oxide surface into bulk silicon. The depth of the H+ implantation determines the thickness of silicon above the buried oxide. Wafers A and B are cleaned and temperature bonded face-to-face. The bonded wafers are annealed, during which time the implanted H+ forms a gas and Wafer A delaminates near the peak of the implanted H+. Wafer B, which now has the buried oxide layer becomes the SOI wafer, while Wafer A becomes the sacrificial wafer. Wafer A, which is now thinner than before the wafer bonding process, can be used in another wafer bonding process as Wafer B.
The H+ implantation process is relatively long, with implant times taking up to several hours, and detrimentally, the topside and backside of the wafer are left with particle defects. The backside of the wafer typically collects more particle defects relative to the topside, because the backside is subjected to most of the handling and contact with components of the ion implantation chamber and the wafer handling device used to center and place the wafer in the ion implantation chamber. One type of defect results from the wafer's contact with elastomeric components such as the wafer support pedestal in the ion implantation chamber and the wafer handling device used to center and place the wafer in the ion implantation chamber. FIG. 1B illustrates the topside and backside of a wafer after an ion implantation process. In some cases the particle pattern on the backside of the wafer shows an image of the support pedestal or wafer transfer device. The backside of the wafer typically collects more particle defects relative to the topside, because the backside is subjected to most of the handling and contact with components of the ion implantation chamber. State of the art methods to remove post-H+ implant defects are not very effective. A cleaning tool such as a wet bench is used, in which the wafer is immersed in a cleaning liquid such as SC-1 or SC-2. Another state of the art method involves treating the backside of the wafer with an etchant solution (such as hydrofluoric acid) because a thermal silicon oxide film layer is formed on the backside of the donor wafer (i.e., Wafer A) during the initial oxidation process prior to ion implantation. The idea is to “lift off” the particle defects by etching the silicon oxide film layer below the particle defects. Instead, the particle defects micromask the silicon oxide from the etchant solution to form small islands or mesas of particle defect/silicon oxide layers on the backside.